/* PUCCI_TEST */
`timescale 1ns/1ns

module PUCCI_TEST;
reg clock,reset;
reg [3:0] PortIn;
wire [3:0] PortOut;
parameter	STEP=100;
	TOP TOP(clock,reset,PortIn,PortOut);
	always	#(STEP/2)	clock=~clock;
	initial begin
			clock=0;reset=0;PortIn=4'h0;
		#100	reset=1;
		#5000	$finish;
	end

initial begin
//	$display("TIME clock reset PortOut");
	$monitor($time,,"%b %b %b %b %b %b %b %b %b %b ",clock,reset,PortOut,TOP.pucci.decoder.loadPC,TOP.pucci.pc.q,TOP.pucci.alu.sum[4:0],TOP.pucci.decoder.DecOut,TOP.pucci.decoder.state,TOP.pucci.decoder.nextstate,TOP.pucci.D_BUS);
//	$monitor($time,,"%b %b %b %b %b %b %b %b %b %b ",clock,reset,PortOut,TOP.pucci.pc.load,TOP.pucci.decoder.loadOut,TOP.pucci.decoder.loadPC,TOP.pucci.pc.q,TOP.pucci.decoder.Fcode,TOP.pucci.alu.sum[3:0],TOP.pucci.decoder.DecOut,TOP.pucci.alu.flagC);
end
endmodule