// program counter
module pc(clock, reset, load, d[11:0], q);
   input        clock, reset, load;
   input [11:0]	d;
   output [11:0] q;


   reg [11:0] 	regQ;
   assign 	q = regQ;

   always @ (posedge clock or negedge reset) begin
      if (!reset)
	regQ <= 12'b000000000000;
      else if (~load)
	regQ <= d;
      else
	regQ <= regQ + 1;
   end
endmodule // pc