module decoder ( clock, reset, D_BUS, flagC, MuxSel, loadA, loadB, loadOut, 
    loadPC, DecOut );
input  [7:0] D_BUS;
output [1:0] MuxSel;
output [11:0] DecOut;
input  clock, reset, flagC;
output loadA, loadB, loadOut, loadPC;
    wire nextstate, state, n10, n11, n12, n13, n14, n15, 
        n16, n17, n18, n19, n20, n21, n22, n23, n24,
        n25,n27,n28,n29;
    dffn \DecOut_reg[5]  ( .d(D_BUS[5]), .cn(loadPC), .rst(reset), .q(DecOut[5]) );
    dffn \DecOut_reg[0]  ( .d(D_BUS[0]), .cn(loadPC), .rst(reset), .q(DecOut[0]) );
    dffn \DecOut_reg[1]  ( .d(D_BUS[1]), .cn(loadPC), .rst(reset), .q(DecOut[1]) );
    dffn \DecOut_reg[2]  ( .d(D_BUS[2]), .cn(loadPC), .rst(reset), .q(DecOut[2]) );
    dffn \DecOut_reg[6]  ( .d(D_BUS[6]), .cn(loadPC), .rst(reset), .q(DecOut[6]) );
    dffn \DecOut_reg[3]  ( .d(D_BUS[3]), .cn(loadPC), .rst(reset), .q(DecOut[3]) );
    dffn \DecOut_reg[7]  ( .d(D_BUS[7]), .cn(loadPC), .rst(reset), .q(DecOut[7]) );
    dffn \DecOut_reg[4]  ( .d(D_BUS[4]), .cn(loadPC), .rst(reset), .q(DecOut[4]) );
//    dffnset reg1 ( .d(n17), .cn(clock), .set(reset), .q(loadPC) );
    dffnset reg1 ( .d(n29), .cn(clock), .set(reset), .q(loadPC) );
    or U10 ( MuxSel[0],D_BUS[4],D_BUS[7] );
    or U11 (n10,D_BUS[6],D_BUS[7]);
    not U12 (n11,D_BUS[6]);
    or U13 (n12,n11,D_BUS[7]);
    not U14 (n13,D_BUS[7]);
    or U15 (n14,D_BUS[6],n13);
    not U16 (n15,D_BUS[4]);
    and U17 (n16,n15,n23);
    or U18 (n17,n11,n13,n16);
    nor U19 (n18,state,n17);
    or U20 (loadA,n10,state);
    or U21 (loadB,n12,state);
    or U22 (loadOut,n14,state);
    not U23 (n24,D_BUS[5]);
    not U24 (MuxSel[1],n24);
    dff reg2 (.d(n18),.cp(clock),.rst(reset),.q(state));
    dff reg11 (.d(D_BUS[3]),.cp(clock),.rst(reset),.q(n19));
    dff reg12 (.d(D_BUS[2]),.cp(clock),.rst(reset),.q(n20));
    dff reg13 (.d(D_BUS[1]),.cp(clock),.rst(reset),.q(n21));
    dff reg14 (.d(D_BUS[0]),.cp(clock),.rst(reset),.q(n22));
    mx21d0 SEL1 ( .i0(D_BUS[0]), .i1(n22), .s(state), .z(DecOut[8]) );
    mx21d0 SEL2 ( .i0(D_BUS[1]), .i1(n21), .s(state), .z(DecOut[9]) );
    mx21d0 SEL3 ( .i0(D_BUS[2]), .i1(n20), .s(state), .z(DecOut[10]) );
    mx21d0 SEL4 ( .i0(D_BUS[3]), .i1(n19), .s(state), .z(DecOut[11]) );
    dff reg15 (.d(flagC),.cp(clock),.rst(reset),.q(n23));
    dffset reg16 (.d(n26),.cp(clock),.set(reset),.q(n27));
    not U25 (n25,n17);
    nand U26 (n26,loadPC,n25);
    not U27 (n28,n27);
    nand U28 (n29,loadPC,n28);
endmodule


module mx21d0 ( i0, i1, s, z);
input i0, i1, s;
output z;
wire z0,z1,zsn;
    not U1 (zsn, s);
    and U2 ( z0, i0, zsn);
    and U3 ( z1, i1, s);
    or U4 ( z, z0, z1);
endmodule

module dff (d, cp, rst, q);
input d, cp, rst;
output q;
reg q;
    always @(posedge cp or negedge rst)
        q <= (!rst)? 0: d;
endmodule

module dffn (d, cn, rst, q);
input d, cn, rst;
output q;
reg q;
    always @(negedge cn or negedge rst)
        q <= (!rst)? 0: d;
endmodule

module dffnset (d, cn, set, q);
input d, cn, set;
output q;
reg q;
    always @(negedge cn or negedge set)
        q <= (!set)? 1: d;
endmodule

module dffset (d, cp, set, q);
input d, cp, set;
output q;
reg q;
    always @(posedge cp or negedge set)
        q <= (!set)? 1: d;
endmodule