module pucci(clock, reset, PortIn,D_BUS, PortOut,A_BUS);
   input	clock, reset;
   input [3:0] 	PortIn;
   input [7:0]	D_BUS;
   output [3:0] PortOut;
   output [11:0] A_BUS;

   wire  	loadA, loadB, loadOut, loadPC, FlagC;
   wire [3:0] 	qA, qB;
   wire [1:0] 	MuxSel;
   wire [3:0] 	MuxOut;
   wire [3:0] 	Result;
   wire [11:0] 	DecOut;
//   wire	[2:0]	Fcode;
   
   decoder decoder(clock,reset,D_BUS[7:0], FlagC, MuxSel, loadA, loadB, loadOut, loadPC, DecOut[11:0]);
//   rom rom(address, data);
   mux mux(MuxSel, qA, qB, PortIn, 4'h0, MuxOut);
   alu alu(clock,reset, MuxOut, DecOut[11:8], Result[3:0], FlagC);

   register A(  clock, reset, loadA,   Result[3:0], qA);
   register B(  clock, reset, loadB,   Result[3:0], qB);
   register Out(clock, reset, loadOut, Result[3:0], PortOut);
   pc pc(       clock, reset, loadPC,  DecOut[11:0], A_BUS);
endmodule // pucci